Learn Makefile by Examples
GNU Make 4.xMake is a build automation tool that automatically builds executable programs and libraries from source code by reading files called Makefiles which specify how to derive the target program.
These examples cover the essential components of Makefiles, including defining targets, using variables and patterns, managing dependencies, and utilizing advanced features like functions and conditionals.
Targets
A target is usually the name of a file that is generated by a program. This sample shows the basic syntax of a rule.
Variables
Variables allow you to define text strings once and substitute them in multiple places. This example demonstrates assignment and usage.
Patterns
Pattern rules allow you to define a generic rule for many files. This sample shows how to compile all .c files to .o files.
Dependencies
Managing dependencies ensures that changing a header file triggers a recompile. This example shows how to track header dependencies.
Phony Targets
Phony targets are targets that are not files. This sample explains why and how to use `.PHONY`.
Macros
Macros (variables) can be assigned in different ways. This example clarifies `=`, `:=`, `?=`, and `+=`.
Rules
Implicit rules are built-in rules that Make knows. This sample shows how to leverage and override them.
Wildcards
Wildcards allow you to select files based on patterns. This example shows how to use `*` and the `wildcard` function.
Functions
Make provides functions for text processing and file manipulation. This sample demonstrates `shell`, `subst`, `foreach`, and `if`.
Conditional Blocks
Directives like `ifdef`, `ifeq`, and `else` control what part of the Makefile is seen by Make. This example shows conditional configuration.